DesignCon
February 24-26, 2026
Location: Santa Clara Convention Center
Presenter: Brad Turcott, Senior Director, Field Application Engineering
Panel: CPO vs. OIO: Evolution or Revolution in Optical Interconnects?
Abstract: As datacenter and AI workloads push the limits of electrical I/O, two optical interconnect paradigms are emerging: Co-Packaged Optics (CPO) and Optical I/O (OIO). CPO integrates optics next to the switch ASIC to reduce power and latency, while OIO goes further—embedding photonics directly into compute packages for chip-to-chip optical communication.
This panel will debate whether OIO is a revolutionary shift that will leapfrog CPO, or simply the next step in optical integration. Experts from across the ecosystem will explore the technical, economic, and deployment trade-offs of each approach, including energy efficiency, packaging complexity, and use-case alignment.
Attendees will hear contrasting views from hyperscalers, chipmakers, and photonics innovators, offering a comprehensive look at the future of optical interconnects. Expect a lively, data-driven discussion on whether the industry is ready to cut the copper cord—or if evolution will win over revolution.
Date: February 24, 2026
Time: 4:45 PM
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Presenter: Marianne Nourzad, Senior Photonics Characterization Engineer
Title: Navigating the New Frontier: A Guide to Testing Silicon Photonics High-Speed Links
Abstract: In recent years, Silicon Photonics (SiPho) high-speed interconnects have emerged as a pivotal technology for meeting increasing bandwidth and efficiency requirements in data communication systems. While traditional electrical High-Speed I/O (HSIO) standards such as PCIe and Ethernet/OIF-CEI have well-established testing methodologies, SiPho-based links present unique testing challenges due to their hybrid electronic-photonic nature.
This paper compares the architecture of conventional HSIO links with silicon photonics solutions, while highlighting their differences and similarities. Key performance metrics including Bit Error Rate (BER), jitter, optical insertion loss, and Optical Modulation Amplitude (OMA) are explored. Detailed test methodologies tailored specifically for SiPho links will be presented, addressing the complexities of optical alignment, thermal stability, and electro-optical co-design and simulation. Laboratory measurements demonstrate the adaptation of conventional HSIO testing frameworks, including eye diagram analysis and jitter decomposition, to the SiPho domain. Further, the importance of multi-stage testing, from wafer-level verification to packaged transceiver characterization, is discussed.
By providing a comprehensive overview and practical guidelines for validating transmitter and receiver performance, this work aims to bridge the gap between established HSIO testing techniques and the unique requirements of advanced silicon photonics integration.
Date: February 26, 2026
Time: 11:15 AM
About DesignCon:
DesignCon is the premier annual Silicon Valley conference and expo for chip, board, and systems engineers, focusing on high-speed communications, signal/power integrity, and electronic design. It features 100+ technical sessions, tutorials, and a large exhibition hall with the latest design tools.
Learn more about our solutions:
Passage L200 3D CPO (co-packaged optics) Passage M1000 Superchip (active photonic interposer)