Passage enables massive bandwidth for die-to-die, chip-to-chip, and system-to-system.  This is the way to build future AI solutions.



Next generation data centers for AI and HPC demand unprecedented performance density that requires extremely high bandwidth I/O in chip designs.   

Passage technology enables direct 3D integration of numerous customer ASIC chiplets (GPU’s, accelerators, etc.)  onto a multi-reticle optical ‘interposer’, enabling massive bandwidth photonic communication at maximum radix.  Coupled with ultra-dense fiber attach and fully integrated control circuitry, Passage delivers the scaling required for the most demanding next-generation applications including trillion-parameter LLMs and AGI.


Dramatic interconnect density improvement driving greater than 10X I/O bandwidth and 100X in 5 years.

More than 30X increase in radix delivering the solution for 1 million node clusters.

Silicon area per package is growing exponentially.  Passage supports greater than 15x the largest packages.

Passage enables supercomputers with a million nodes (xPU’s) and beyond.


Fully integrated chiplet interconnect solution with direct fiber attach all in a single package.

Uniform architecture for flexible dicing (e.g. 1×1, 2×2, 2×4).

High bandwidth I/O interconnects high performance CPUs, GPUs, FPGAs, DRAM, and ASICs in a single 3D package.

Integrated photonics and control electronics provide the most efficient channels and deliver the highest performance density.

Built-in reconfigurable OCS (Optical Circuit Switch) and control mechanism enabling redundancy and increasing reliability of the design.

WDM modulation enables multi-lambda bidirectional optical transmit and receive on a single waveguide or fiber, multiplying communication bandwidth.

Large scale AI/ML Training and Inferencing – Directly scale GPU/Accelerator clusters up to a million nodes and beyond with integrated optical connectivity.

Datacenter Networking – Scale switch silicon solutions up to hundreds of Tbps with multi-die optical connectivity.

HPC – Massively expand I/O performance of large-scale compute clusters.

Hardware Emulation – Seamlessly and flexibly integrate large numbers of programmable elements with unprecedented bandwidth.

Massive Bandwidth Density – Customer ASICs no longer shoreline-limited.  3D integration allows efficient high-speed SerDes to be located anywhere on the ASIC die.

Optimized Workload Performance – Build the largest direct-connect domain leveraging dense WDM optical network and high-density fiber attach.  

Comprehensive Resiliency and Flexibility  – Reconfigurable waveguide network with integrated OCS can be adjusted in response to infrastructure failures or to optimize workload performance and multi-tenancy.

Reduced Complexity – Customer ASIC chiplets directly connected via wires or waveguides in Passage – eliminates “rat’s nests” of fibers that plague CPO chiplet-based solutions.

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