Jul 7–10, 2025
San Jose, CA

CHIPcon 2025

San Jose Marriott

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Session: SESSION 6: Optical Interconnect & Silicon Photonics

Title: Silicon Photonics and Chiplet Integration for Future Compute Platforms

Speaker: Sandeep Sane, Sr. Director, Head of Packaging, Lightmatter 

San Jose Marriott  |  San Jose, California

Description: Silicon Photonics enables high-speed, energy-efficient data transfer, while Advanced Packaging—including 2.5D/3D integration and chiplet architectures—enhances performance, thermal management, and interconnect density.

This session explores how these complementary technologies are reshaping high-performance computing. We’ll discuss their current maturity, integration pathways, and key challenges to large-scale deployment. Together, they provide the foundation needed to meet the compute and bandwidth demands of an AI-driven future.

When and Where: 

Date: Thursday July 10, 2025 

Time: 1:30 PM – 2:30 PM

Location: San Jose Marriott – San Jose, CA

About CHIPcon 2025:

The IMAPS CHIPcon conference will be held July 7-10, 2025, at the San Jose Marriott in San Jose California, and will focus exclusively on the innovative device integration approaches, technology developments, solutions, and business trends enabling the continued advancement in semiconductor device (system) performance. CHIPcon 2025 will offer cutting-edge presentations from scientists, technologists and business leaders across the globe with expertise in high performance computing, networking, automotive, cellular, and mobile market (consumer) segments. 

The conference will explore the current state of the art in design, simulation, packaging, test, process, and material technologies supporting the integration and delivery of a complete semiconductor system or subsystem solution.  Attendees will be exposed to thought-provoking advanced device and package structures with high functioning system performance, mechanical reliability, thermal management and high yield manufacturability.

Learn more about our solutions:
Passage L200 3D CPO (co-packaged optics) Passage M1000 Superchip (active photonic interposer)

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