Electronic Design Process Symposium 2025
Title: Future Compute Platforms through Silicon Photonics and Advanced Chiplet Packaging
Presenter: Sandeep Sane, Sr. Director, Head of Packaging Technologies
Abstract: The exponential growth of high-performance computing—driven by AI and other data-intensive applications—is pushing traditional semiconductor technologies to their limits, as Moore’s Law and Dennard Scaling slow. Silicon Photonics offers a breakthrough path forward, enabling faster, more energy-efficient data transmission that reduces latency and power usage in next-generation data centers. In parallel, advanced packaging approaches—such as 2.5D/3D integration and chiplet architectures—tackle power, thermal, and performance bottlenecks by increasing interconnect density and silicon efficiency. This talk explores how these two technologies complement each other to meet future computing demands. We will emphasize the importance of an error-free design philosophy and the need to leverage multi-physics analysis—spanning optical, signal integrity, power integrity, thermal, and mechanical domains—to deliver robust, high-volume-ready designs. The discussion will cover the current state of the art, ongoing integration efforts, and key industry challenges that must be addressed to achieve scalable adoption.
When and Where:
Date: Thursday, October 2nd, 2025
Time: 10:00 AM PT
Location: SEMI – 673 South Milpitas Boulevard Milpitas, CA 95035
About EDPS: EDPS is a leading forum for advanced chip and systems design process development as well as CAD methodologies and addresses EDA, foundry and design industries design and manufacturing challenges. This annual gathering of electronic IC/system designers, developers, and manufacturing experts will discuss design methodologies, design flows and CAD tool needs via keynotes and session presentations in following areas:
- Agentic AI and Its Application in EDA and Design
- Innovative Design Techniques including HSIO and AI/ML
- 3D IC and Heterogeneous Integration (e.g., System Design, EDA, STCO, Packaging, UCIe)
- AI Architecture and Application of AI/ML in EDA and Design
Learn more about our solutions:
Passage L200 3D CPO (co-packaged optics) Passage M1000 Superchip (active photonic interposer)