Photonic
Chips
for AI

Chips are becoming physically larger and more power hungry due to fundamental, physical limitations of transistors. Compute performance roadmaps are now defined by silicon-area-per-package and the number of processors tightly linked in a high bandwidth scale-up domain. The quest for AGI is driving this trend at warp speed.

Chip scale over time

1X
2000
2010
2020
2030
SILICON AREA PER CHIP
(MM2)

A bright foundation for big chips

We enable the silicon-area-per-package scaling roadmap, shatter the concept of “beachfront” and bring networking radices to new highs with our breakthrough interconnect and packaging technology platform—Passage. We sell the photonic chips that will make building AGI possible (and the lasers that power them). From single reticle to wafer-scale, the world’s fastest (and first) 3D-stacked photonic chips.

High Performance Customer ASIC Chiplets
Passage
(Reconfigurable Optical Interposer with Integrated Controller)
Bi-Directional Pluggable High Density Fiber Array
Substrate

This is the way (follow me).

We partner with companies that build high-performance chips (like GPUs and switches) to achieve extreme scaling. Connect hundreds to millions of chips together in a single, high bandwidth, low latency interconnect domain. At Lightmatter, we’re blurring the line between scale-up and scale-out networks.

Lightmatter and ASIC partner send design databases to the silicon foundries for wafer fabrication.

The silicon foundries send the photonics and digital wafers that are transported to the OSAT.

These wafers are diced and the silicon is assembled together in a package to produce Passage-enabled chips.

The OSAT transports these chips to an ODM for system assembly.

The ODM builds the server hardware platforms and transports them to the hyperscaler (i.e. data center).